DESIGN OF FAST AND EFFICIENT HYBRID-FPGAs FOR NUMERICALLY INTENSIVE APPLICATIONS IN FLUID DYNAMICS AND IMAGE/VIDEO PROCESSING

Numerical simulations in Computational Fluid Dynamics, involves modules solving sets of equations (2nd-order Crank-Nicolson/Adams-Bashforth, 3rd-order Runge-Kutta time-stepping etc.) which have some common computation features, and performed iteratively. Similarly video and image processing applications involve tasks (mosaic building to compress video into images, image compression such as DCT, DWT etc.) which also have some common computation features and require iterative processing. Both these domains are known to have a high degree of relevance to military applications. It has been shown by several researchers that these applications are well suited to be executed on spatially parallel processor architectures. FPGAs in particular offer large amounts of on-chip spatial parallel units, thus capable of performing orders of magnitude faster than regular serial processors. But FPGAs suffer from the drawbacks of being application agnostic and hence incur penalties of loss of clock cycles in redundant reconfigurations, generic routing and poor memory architectures which impact speed, power and silicon area. All these factors have led us into exploring the reconfigurable architecture design space with the application domain being prioritized. This paper focuses on the extraction of tasks or core clusters in Control Data Flow Graphs (CDFGs) of multimedia and fluid dynamics applications followed by designing the architecture to embed them in Hybrid-FPGA environments. By Hybrid, we mean that the proposed FPGA architectures will involve LUT regions, ASIC regions and possibly VPGA regions. Tasks or core clusters obtained through the common sub-graph analysis between basic blocks within and across routines are basically recurring computation patterns implemented as ASICs on non-reconfigurable area. After removing the common sub-graphs from the CDFG, remaining parts of each basic block are then implemented on LUT based reconfigurable area. A Packing mechanism designed to improve the routing architecture by reducing the switching requirements by 12-20% has been proposed. This mechanism, for configurable logic uses live-in live-out variable analysis and scheduling information of CDFGs in its cost function in addition to routability and timing driven cost metrics defined by other researchers. We have conducted experiments on several complex routines from the target applications. Map/synthesis reports based on Xilinx architectures were obtained. Results show that partial reconfiguration with the use of computation cores embedded in a sea of LUTs offer the potential for massive savings in gate density. In addition to that, by eliminating the need for unnecessary and redundant sub-circuit pattern configurations, switching requirements in configurable area is reduced due to localization of global …